Branch data Line data Source code
1 : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
2 : : /*
3 : : * Physical memory map
4 : : *
5 : : * Copyright 2017-2019 IBM Corp.
6 : : */
7 : :
8 : : #include <phys-map.h>
9 : : #include <chip.h>
10 : : #include <skiboot.h>
11 : : #include <opal-api.h>
12 : : #include <stack.h>
13 : : #include <inttypes.h>
14 : :
15 : : struct phys_map_entry {
16 : : enum phys_map_type type;
17 : : int index;
18 : : uint64_t addr;
19 : : uint64_t size;
20 : : };
21 : :
22 : : struct phys_map_info {
23 : : int chip_select_shift;
24 : : const struct phys_map_entry *table;
25 : : };
26 : :
27 : : static const struct phys_map_info *phys_map;
28 : :
29 : : static const struct phys_map_entry phys_map_table_p10[] = {
30 : : /* System memory upto 4TB minus GPU memory */
31 : : { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },
32 : :
33 : : /* Configure OpenCapi memory as before with the old chips.
34 : : * Keep in mind that we would need to rework this by allocating
35 : : * a new topology id.
36 : : */
37 : : { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull },
38 : : { OCAPI_MEM, 1, 0x0002040000000000ull, 0x0000040000000000ull },
39 : :
40 : : /* 0 TB offset @ MMIO 0x0006000000000000ull */
41 : : { PHB5_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },
42 : : { PHB5_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },
43 : : { PHB5_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },
44 : : { PHB5_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },
45 : : { PHB5_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },
46 : : { PHB5_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },
47 : : { PHB5_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },
48 : : { PHB5_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },
49 : : { PHB5_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },
50 : : { PHB5_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull },
51 : : { PHB5_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull },
52 : : { PHB5_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull },
53 : : { PHB5_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull },
54 : : { PHB5_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull },
55 : : { PHB5_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull },
56 : : { PHB5_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull },
57 : : { PHB5_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull },
58 : : { PHB5_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull },
59 : : { PHB5_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull },
60 : : { PHB5_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull },
61 : : { PHB5_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull },
62 : : { RESV , 0, 0x000600c3c0600000ull, 0x0000003c3fa00000ull },
63 : :
64 : : /* 1 TB offset */
65 : : { RESV , 1, 0x0006010000000000ull, 0x0000010000000000ull },
66 : :
67 : : /* 2 TB offset */
68 : : { PHB5_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },
69 : : { PHB5_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },
70 : : { PHB5_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },
71 : : { RESV , 2, 0x000602c000000000ull, 0x0000004000000000ull },
72 : :
73 : : /* 3 TB offset */
74 : : { LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull },
75 : : { FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull },
76 : : { XIVE_IC , 0, 0x0006030200000000ull, 0x0000000002000000ull },
77 : : { PSIHB_ESB , 0, 0x0006030202000000ull, 0x0000000000100000ull },
78 : : { RESV , 3, 0x0006030202100000ull, 0x0000000000f00000ull },
79 : : { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
80 : : { RESV , 4, 0x0006030203100000ull, 0x0000000000080000ull },
81 : : { XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull },
82 : : { RESV , 5, 0x00060302031c0000ull, 0x0000000000010000ull },
83 : : { NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull },
84 : : { RESV , 6, 0x00060302031e0000ull, 0x0000000004e20000ull },
85 : : { XIVE_NVC , 0, 0x0006030208000000ull, 0x0000000008000000ull },
86 : : { RESV , 7, 0x0006030210000000ull, 0x00000000ee000000ull },
87 : : { VAS_HYP_WIN , 0, 0x00060302fe000000ull, 0x0000000002000000ull },
88 : : { VAS_USER_WIN , 0, 0x0006030300000000ull, 0x0000000100000000ull },
89 : :
90 : : /* TODO: MC, OCMB */
91 : : { RESV , 8, 0x0006030400000000ull, 0x0000008400000000ull },
92 : : { PAU_OCAPI_MMIO , 0, 0x0006038800000000ull, 0x0000000800000000ull },
93 : : { PAU_OCAPI_MMIO , 1, 0x0006039000000000ull, 0x0000000800000000ull },
94 : : { PAU_OCAPI_MMIO , 2, 0x0006039800000000ull, 0x0000000800000000ull },
95 : : { PAU_OCAPI_MMIO , 3, 0x000603a000000000ull, 0x0000000800000000ull },
96 : : { PAU_OCAPI_MMIO , 4, 0x000603a800000000ull, 0x0000000800000000ull },
97 : : { PAU_OCAPI_MMIO , 5, 0x000603b000000000ull, 0x0000000800000000ull },
98 : : { PAU_OCAPI_MMIO , 6, 0x000603b800000000ull, 0x0000000800000000ull },
99 : : { PAU_OCAPI_MMIO , 7, 0x000603c000000000ull, 0x0000000800000000ull },
100 : : { PAU_OCAPI_MMIO , 8, 0x000603c800000000ull, 0x0000000800000000ull },
101 : : { PAU_OCAPI_MMIO , 9, 0x000603d000000000ull, 0x0000000800000000ull },
102 : : { PAU_OCAPI_MMIO ,10, 0x000603d800000000ull, 0x0000000800000000ull },
103 : : { PAU_OCAPI_MMIO ,11, 0x000603e000000000ull, 0x0000000800000000ull },
104 : : { PAU_REGS , 0, 0x000603e800000000ull, 0x0000000001000000ull },
105 : : { PAU_REGS , 1, 0x000603e801000000ull, 0x0000000001000000ull },
106 : : { PAU_REGS , 2, 0x000603e802000000ull, 0x0000000001000000ull },
107 : : { PAU_REGS , 3, 0x000603e803000000ull, 0x0000000001000000ull },
108 : : { PAU_REGS , 4, 0x000603e804000000ull, 0x0000000001000000ull },
109 : : { PAU_REGS , 5, 0x000603e805000000ull, 0x0000000001000000ull },
110 : : { RESV , 9, 0x000603e806000000ull, 0x0000000000040000ull },
111 : : { PAU_NTL , 0, 0x000603e806040000ull, 0x0000000000020000ull },
112 : : { PAU_NTL , 1, 0x000603e806060000ull, 0x0000000000020000ull },
113 : : { PAU_GENID , 0, 0x000603e806080000ull, 0x0000000000080000ull },
114 : : { RESV ,10, 0x000603e806100000ull, 0x0000000000040000ull },
115 : : { PAU_NTL , 2, 0x000603e806140000ull, 0x0000000000020000ull },
116 : : { PAU_NTL , 3, 0x000603e806160000ull, 0x0000000000020000ull },
117 : : { PAU_GENID , 1, 0x000603e806180000ull, 0x0000000000080000ull },
118 : : { RESV ,11, 0x000603e806200000ull, 0x0000000000040000ull },
119 : : { PAU_NTL , 4, 0x000603e806240000ull, 0x0000000000020000ull },
120 : : { PAU_NTL , 5, 0x000603e806260000ull, 0x0000000000020000ull },
121 : : { PAU_GENID , 2, 0x000603e806280000ull, 0x0000000000080000ull },
122 : : { RESV ,12, 0x000603e806300000ull, 0x0000000000040000ull },
123 : : { PAU_NTL , 6, 0x000603e806340000ull, 0x0000000000020000ull },
124 : : { PAU_NTL , 7, 0x000603e806360000ull, 0x0000000000020000ull },
125 : : { PAU_GENID , 3, 0x000603e806380000ull, 0x0000000000080000ull },
126 : : { RESV ,13, 0x000603e806400000ull, 0x0000000000040000ull },
127 : : { PAU_NTL , 8, 0x000603e806440000ull, 0x0000000000020000ull },
128 : : { PAU_NTL , 9, 0x000603e806460000ull, 0x0000000000020000ull },
129 : : { PAU_GENID , 4, 0x000603e806480000ull, 0x0000000000080000ull },
130 : : { RESV ,14, 0x000603e806500000ull, 0x0000000000040000ull },
131 : : { PAU_NTL ,10, 0x000603e806540000ull, 0x0000000000020000ull },
132 : : { PAU_NTL ,11, 0x000603e806560000ull, 0x0000000000020000ull },
133 : : { PAU_GENID , 5, 0x000603e806580000ull, 0x0000000000080000ull },
134 : : { RESV ,15, 0x000603e806600000ull, 0x00000013F9A00000ull },
135 : : { XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull },
136 : :
137 : : /* 4 TB offset */
138 : : { XIVE_NVPG , 0, 0x0006040000000000ull, 0x0000010000000000ull },
139 : :
140 : : /* 5 - 7 TB offset */
141 : : /* for P10 the END and ESB regions are separate in the MMIO
142 : : * table */
143 : : { XIVE_ESB , 0, 0x0006050000000000ull, 0x0000010000000000ull },
144 : : { XIVE_END , 0, 0x0006060000000000ull, 0x0000020000000000ull },
145 : :
146 : : /* 8 - 13 TB offset */
147 : : { RESV ,16, 0x0006080000000000ull, 0x0000060000000000ull },
148 : :
149 : : /* 14 TB offset */
150 : : { RESV ,17, 0x00060e0000000000ull, 0x0000008000000000ull },
151 : :
152 : : { NULL_MAP, 0, 0, 0 },
153 : : };
154 : :
155 : : static const struct phys_map_entry phys_map_table_nimbus[] = {
156 : :
157 : : /* System memory upto 4TB minus GPU memory */
158 : : { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },
159 : : /* GPU memory from 4TB - 128GB*GPU */
160 : : { GPU_MEM_4T_DOWN, 5, 0x0000034000000000ull, 0x0000002000000000ull },
161 : : { GPU_MEM_4T_DOWN, 4, 0x0000036000000000ull, 0x0000002000000000ull },
162 : : { GPU_MEM_4T_DOWN, 3, 0x0000038000000000ull, 0x0000002000000000ull },
163 : : { GPU_MEM_4T_DOWN, 2, 0x000003a000000000ull, 0x0000002000000000ull },
164 : : { GPU_MEM_4T_DOWN, 1, 0x000003c000000000ull, 0x0000002000000000ull },
165 : : { GPU_MEM_4T_DOWN, 0, 0x000003e000000000ull, 0x0000002000000000ull },
166 : : /* GPU memory from 4TB + 128GB*GPU. 4 GPUs only */
167 : : { GPU_MEM_4T_UP, 0, 0x0000040000000000ull, 0x0000002000000000ull },
168 : : { GPU_MEM_4T_UP, 1, 0x0000042000000000ull, 0x0000002000000000ull },
169 : : { GPU_MEM_4T_UP, 2, 0x0000044000000000ull, 0x0000002000000000ull },
170 : : { GPU_MEM_4T_UP, 3, 0x0000046000000000ull, 0x0000002000000000ull },
171 : :
172 : : /*
173 : : * OpenCAPI LPC Memory
174 : : *
175 : : * With chip address extension enabled, we allocate 4TB ranges
176 : : * (in the second non-mirrored region) for each OpenCAPI link
177 : : * by varying the upper 2 bits of the group ID.
178 : : *
179 : : * We don't currently support >4TB ranges.
180 : : */
181 : : { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull },
182 : : { OCAPI_MEM, 1, 0x0002800000000000ull, 0x0000040000000000ull },
183 : : { OCAPI_MEM, 2, 0x0003000000000000ull, 0x0000040000000000ull },
184 : : { OCAPI_MEM, 3, 0x0003800000000000ull, 0x0000040000000000ull },
185 : :
186 : : /* 0 TB offset @ MMIO 0x0006000000000000ull */
187 : : { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },
188 : : { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },
189 : : { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },
190 : : { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },
191 : : { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },
192 : : { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },
193 : : { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },
194 : : { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },
195 : : { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },
196 : : { PHB4_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull },
197 : : { PHB4_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull },
198 : : { PHB4_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull },
199 : : { PHB4_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull },
200 : : { PHB4_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull },
201 : : { PHB4_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull },
202 : : { PHB4_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull },
203 : : { PHB4_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull },
204 : : { PHB4_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull },
205 : : { PHB4_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull },
206 : : { PHB4_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull },
207 : : { PHB4_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull },
208 : : { RESV , 0, 0x000600c3c0600000ull, 0x0000000c3fa00000ull },
209 : : { NPU_OCAPI_MMIO , 0, 0x000600d000000000ull, 0x0000000800000000ull },
210 : : { NPU_OCAPI_MMIO , 1, 0x000600d800000000ull, 0x0000000800000000ull },
211 : : { NPU_OCAPI_MMIO , 2, 0x000600e000000000ull, 0x0000000800000000ull },
212 : : { NPU_OCAPI_MMIO , 3, 0x000600e800000000ull, 0x0000000800000000ull },
213 : : { NPU_OCAPI_MMIO , 4, 0x000600f000000000ull, 0x0000000800000000ull },
214 : : { NPU_OCAPI_MMIO , 5, 0x000600f800000000ull, 0x0000000800000000ull },
215 : :
216 : : /* 1 TB offset @ MMIO 0x0006000000000000ull */
217 : : { XIVE_VC , 0, 0x0006010000000000ull, 0x0000008000000000ull },
218 : : { XIVE_PC , 0, 0x0006018000000000ull, 0x0000001000000000ull },
219 : : { VAS_USER_WIN , 0, 0x0006019000000000ull, 0x0000000100000000ull },
220 : : { VAS_HYP_WIN , 0, 0x0006019100000000ull, 0x0000000002000000ull },
221 : : { RESV , 1, 0x0006019102000000ull, 0x000000001e000000ull },
222 : : { OCAB_XIVE_ESB , 0, 0x0006019120000000ull, 0x0000000020000000ull },
223 : : { RESV , 3, 0x0006019140000000ull, 0x0000006ec0000000ull },
224 : :
225 : : /* 2 TB offset @ MMIO 0x0006000000000000ull */
226 : : { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },
227 : : { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },
228 : : { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },
229 : : { RESV , 4, 0x000602c000000000ull, 0x0000004000000000ull },
230 : :
231 : : /* 3 TB offset @ MMIO 0x0006000000000000ull */
232 : : { LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull },
233 : : { FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull },
234 : : { NPU_REGS , 0, 0x0006030200000000ull, 0x0000000001000000ull },
235 : : { NPU_USR , 0, 0x0006030201000000ull, 0x0000000000200000ull },
236 : : { NPU_PHY , 0, 0x0006030201200000ull, 0x0000000000200000ull },
237 : : { NPU_PHY , 1, 0x0006030201400000ull, 0x0000000000200000ull },
238 : : { NPU_NTL , 0, 0x0006030201600000ull, 0x0000000000020000ull },
239 : : { NPU_NTL , 1, 0x0006030201620000ull, 0x0000000000020000ull },
240 : : { NPU_NTL , 2, 0x0006030201640000ull, 0x0000000000020000ull },
241 : : { NPU_NTL , 3, 0x0006030201660000ull, 0x0000000000020000ull },
242 : : { NPU_NTL , 4, 0x0006030201680000ull, 0x0000000000020000ull },
243 : : { NPU_NTL , 5, 0x00060302016a0000ull, 0x0000000000020000ull },
244 : : { NPU_GENID , 0, 0x00060302016c0000ull, 0x0000000000020000ull },
245 : : { NPU_GENID , 1, 0x00060302016e0000ull, 0x0000000000020000ull },
246 : : { NPU_GENID , 2, 0x0006030201700000ull, 0x0000000000020000ull },
247 : : { RESV , 5, 0x0006030201720000ull, 0x00000000018e0000ull },
248 : : { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
249 : : { XIVE_IC , 0, 0x0006030203100000ull, 0x0000000000080000ull },
250 : : { XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull },
251 : : { PSIHB_ESB , 0, 0x00060302031c0000ull, 0x0000000000010000ull },
252 : : { NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull },
253 : : { RESV , 6, 0x00060302031e0000ull, 0x000000001ce20000ull },
254 : : { CENTAUR_SCOM , 0, 0x0006030220000000ull, 0x0000000020000000ull },
255 : : { RESV , 7, 0x0006030240000000ull, 0x000000f9c0000000ull },
256 : : { XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull },
257 : :
258 : : /* NULL entry at end */
259 : : { NULL_MAP, 0, 0, 0 },
260 : : };
261 : :
262 : : static const struct phys_map_info phys_map_nimbus = {
263 : : .chip_select_shift = 42,
264 : : .table = phys_map_table_nimbus,
265 : : };
266 : :
267 : : static const struct phys_map_entry phys_map_table_axone[] = {
268 : :
269 : : /* System memory up to 4TB minus GPU memory */
270 : : { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },
271 : : /* GPU memory from 4TB - 128GB*GPU */
272 : : { GPU_MEM_4T_DOWN, 5, 0x0000034000000000ull, 0x0000002000000000ull },
273 : : { GPU_MEM_4T_DOWN, 4, 0x0000036000000000ull, 0x0000002000000000ull },
274 : : { GPU_MEM_4T_DOWN, 3, 0x0000038000000000ull, 0x0000002000000000ull },
275 : : { GPU_MEM_4T_DOWN, 2, 0x000003a000000000ull, 0x0000002000000000ull },
276 : : { GPU_MEM_4T_DOWN, 1, 0x000003c000000000ull, 0x0000002000000000ull },
277 : : { GPU_MEM_4T_DOWN, 0, 0x000003e000000000ull, 0x0000002000000000ull },
278 : :
279 : : /* 0 TB offset @ MMIO 0x0006000000000000ull */
280 : : { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },
281 : : { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },
282 : : { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },
283 : : { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },
284 : : { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },
285 : : { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },
286 : : { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },
287 : : { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },
288 : : { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },
289 : : { PHB4_XIVE_ESB, 0, 0x000600c300000000ull, 0x0000000020000000ull },
290 : : { PHB4_XIVE_ESB, 1, 0x000600c320000000ull, 0x0000000020000000ull },
291 : : { PHB4_XIVE_ESB, 2, 0x000600c340000000ull, 0x0000000020000000ull },
292 : : { PHB4_XIVE_ESB, 3, 0x000600c360000000ull, 0x0000000020000000ull },
293 : : { PHB4_XIVE_ESB, 4, 0x000600c380000000ull, 0x0000000020000000ull },
294 : : { PHB4_XIVE_ESB, 5, 0x000600c3a0000000ull, 0x0000000020000000ull },
295 : : { PHB4_REG_SPC, 0, 0x000600c3c0000000ull, 0x0000000000100000ull },
296 : : { PHB4_REG_SPC, 1, 0x000600c3c0100000ull, 0x0000000000100000ull },
297 : : { PHB4_REG_SPC, 2, 0x000600c3c0200000ull, 0x0000000000100000ull },
298 : : { PHB4_REG_SPC, 3, 0x000600c3c0300000ull, 0x0000000000100000ull },
299 : : { PHB4_REG_SPC, 4, 0x000600c3c0400000ull, 0x0000000000100000ull },
300 : : { PHB4_REG_SPC, 5, 0x000600c3c0500000ull, 0x0000000000100000ull },
301 : : { RESV, 0, 0x000600c3c0600000ull, 0x0000000c3fa00000ull },
302 : : { NPU_OCAPI_MMIO, 0, 0x000600d000000000ull, 0x0000000800000000ull },
303 : : { NPU_OCAPI_MMIO, 1, 0x000600d800000000ull, 0x0000000800000000ull },
304 : : { NPU_OCAPI_MMIO, 2, 0x000600e000000000ull, 0x0000000800000000ull },
305 : : { NPU_OCAPI_MMIO, 3, 0x000600e800000000ull, 0x0000000800000000ull },
306 : : { NPU_OCAPI_MMIO, 4, 0x000600f000000000ull, 0x0000000800000000ull },
307 : : { NPU_OCAPI_MMIO, 5, 0x000600f800000000ull, 0x0000000800000000ull },
308 : :
309 : : /* 1 TB offset @ MMIO 0x0006000000000000ull */
310 : : { XIVE_VC, 0, 0x0006010000000000ull, 0x0000008000000000ull },
311 : : { XIVE_PC, 0, 0x0006018000000000ull, 0x0000004000000000ull },
312 : : { VAS_USER_WIN, 0, 0x000601c000000000ull, 0x0000000100000000ull },
313 : : { VAS_HYP_WIN, 0, 0x000601c100000000ull, 0x0000000002000000ull },
314 : : { RESV, 1, 0x000601c102000000ull, 0x0000003efe000000ull },
315 : :
316 : : /* 2 TB offset @ MMIO 0x0006000000000000ull */
317 : : { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },
318 : : { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },
319 : : { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },
320 : : { RESV, 2, 0x000602c000000000ull, 0x0000004000000000ull },
321 : :
322 : : /* 3 TB offset @ MMIO 0x0006000000000000ull */
323 : : { LPC_BUS, 0, 0x0006030000000000ull, 0x0000000100000000ull },
324 : : { FSP_MMIO, 0, 0x0006030100000000ull, 0x0000000100000000ull },
325 : : { RESV, 3, 0x0006030200000000ull, 0x0000000003000000ull },
326 : : { PSIHB_REG, 0, 0x0006030203000000ull, 0x0000000000100000ull },
327 : : { XIVE_IC, 0, 0x0006030203100000ull, 0x0000000000080000ull },
328 : : { XIVE_TM, 0, 0x0006030203180000ull, 0x0000000000040000ull },
329 : : { PSIHB_ESB, 0, 0x00060302031c0000ull, 0x0000000000010000ull },
330 : : { NX_RNG, 0, 0x00060302031d0000ull, 0x0000000000010000ull },
331 : : { RESV, 4, 0x00060302031e0000ull, 0x00000001fce20000ull },
332 : : { MC_OCMB_CFG, 0, 0x0006030400000000ull, 0x0000000080000000ull },
333 : : { MC_OCMB_CFG, 1, 0x0006030480000000ull, 0x0000000080000000ull },
334 : : { MC_OCMB_MMIO, 0, 0x0006030500000000ull, 0x0000000080000000ull },
335 : : { MC_OCMB_MMIO, 1, 0x0006030580000000ull, 0x0000000080000000ull },
336 : : { MC_OCMB_CFG, 2, 0x0006030600000000ull, 0x0000000080000000ull },
337 : : { MC_OCMB_CFG, 3, 0x0006030680000000ull, 0x0000000080000000ull },
338 : : { MC_OCMB_MMIO, 2, 0x0006030700000000ull, 0x0000000080000000ull },
339 : : { MC_OCMB_MMIO, 3, 0x0006030780000000ull, 0x0000000080000000ull },
340 : : { MC_OCMB_CFG, 4, 0x0006030800000000ull, 0x0000000080000000ull },
341 : : { MC_OCMB_CFG, 5, 0x0006030880000000ull, 0x0000000080000000ull },
342 : : { MC_OCMB_MMIO, 4, 0x0006030900000000ull, 0x0000000080000000ull },
343 : : { MC_OCMB_MMIO, 5, 0x0006030980000000ull, 0x0000000080000000ull },
344 : : { MC_OCMB_CFG, 6, 0x0006030a00000000ull, 0x0000000080000000ull },
345 : : { MC_OCMB_CFG, 7, 0x0006030a80000000ull, 0x0000000080000000ull },
346 : : { MC_OCMB_MMIO, 6, 0x0006030b00000000ull, 0x0000000080000000ull },
347 : : { MC_OCMB_MMIO, 7, 0x0006030b80000000ull, 0x0000000080000000ull },
348 : : { MC_OCMB_CFG, 8, 0x0006030c00000000ull, 0x0000000080000000ull },
349 : : { MC_OCMB_CFG, 9, 0x0006030c80000000ull, 0x0000000080000000ull },
350 : : { MC_OCMB_MMIO, 8, 0x0006030d00000000ull, 0x0000000080000000ull },
351 : : { MC_OCMB_MMIO, 9, 0x0006030d80000000ull, 0x0000000080000000ull },
352 : : { MC_OCMB_CFG, 10, 0x0006030e00000000ull, 0x0000000080000000ull },
353 : : { MC_OCMB_CFG, 11, 0x0006030e80000000ull, 0x0000000080000000ull },
354 : : { MC_OCMB_MMIO, 10, 0x0006030f00000000ull, 0x0000000080000000ull },
355 : : { MC_OCMB_MMIO, 11, 0x0006030f80000000ull, 0x0000000080000000ull },
356 : : { MC_OCMB_CFG, 12, 0x0006031000000000ull, 0x0000000080000000ull },
357 : : { MC_OCMB_CFG, 13, 0x0006031080000000ull, 0x0000000080000000ull },
358 : : { MC_OCMB_MMIO, 12, 0x0006031100000000ull, 0x0000000080000000ull },
359 : : { MC_OCMB_MMIO, 13, 0x0006031180000000ull, 0x0000000080000000ull },
360 : : { MC_OCMB_CFG, 14, 0x0006031200000000ull, 0x0000000080000000ull },
361 : : { MC_OCMB_CFG, 15, 0x0006031280000000ull, 0x0000000080000000ull },
362 : : { MC_OCMB_MMIO, 14, 0x0006031300000000ull, 0x0000000080000000ull },
363 : : { MC_OCMB_MMIO, 15, 0x0006031380000000ull, 0x0000000080000000ull },
364 : : { RESV, 5, 0x0006031400000000ull, 0x000000d800000000ull },
365 : : { NPU_REGS, 0, 0x000603ec00000000ull, 0x0000000001000000ull },
366 : : { NPU_REGS, 1, 0x000603ec01000000ull, 0x0000000001000000ull },
367 : : { NPU_REGS, 2, 0x000603ec02000000ull, 0x0000000001000000ull },
368 : : { NPU_NTL, 0, 0x000603ec03000000ull, 0x0000000000020000ull },
369 : : { NPU_NTL, 1, 0x000603ec03020000ull, 0x0000000000020000ull },
370 : : { NPU_NTL, 2, 0x000603ec03040000ull, 0x0000000000020000ull },
371 : : { NPU_NTL, 3, 0x000603ec03060000ull, 0x0000000000020000ull },
372 : : { NPU_GENID, 0, 0x000603ec03080000ull, 0x0000000000080000ull },
373 : : { NPU_NTL, 4, 0x000603ec03100000ull, 0x0000000000020000ull },
374 : : { NPU_NTL, 5, 0x000603ec03120000ull, 0x0000000000020000ull },
375 : : { NPU_NTL, 6, 0x000603ec03140000ull, 0x0000000000020000ull },
376 : : { NPU_NTL, 7, 0x000603ec03160000ull, 0x0000000000020000ull },
377 : : { NPU_GENID, 1, 0x000603ec03180000ull, 0x0000000000080000ull },
378 : : { NPU_NTL, 8, 0x000603ec03200000ull, 0x0000000000020000ull },
379 : : { NPU_NTL, 9, 0x000603ec03220000ull, 0x0000000000020000ull },
380 : : { NPU_NTL, 10, 0x000603ec03240000ull, 0x0000000000020000ull },
381 : : { NPU_NTL, 11, 0x000603ec03260000ull, 0x0000000000020000ull },
382 : : { NPU_GENID, 2, 0x000603ec03280000ull, 0x0000000000080000ull },
383 : : { RESV, 6, 0x000603ec03300000ull, 0x0000000ffcd00000ull },
384 : : { XSCOM, 0, 0x000603fc00000000ull, 0x0000000400000000ull },
385 : :
386 : : /* NULL entry at end */
387 : : { NULL_MAP, 0, 0, 0 },
388 : : };
389 : :
390 : : static const struct phys_map_info phys_map_axone = {
391 : : .chip_select_shift = 42,
392 : : .table = phys_map_table_axone,
393 : : };
394 : :
395 : : static const struct phys_map_info phys_map_p10 = {
396 : : .chip_select_shift = 44,
397 : : .table = phys_map_table_p10,
398 : : };
399 : :
400 : 14240 : static inline bool phys_map_entry_null(const struct phys_map_entry *e)
401 : : {
402 : 14240 : if (e->type == NULL_MAP)
403 : 9 : return true;
404 : 14231 : return false;
405 : : }
406 : :
407 : :
408 : : /* This crashes skiboot on error as any bad calls here are almost
409 : : * certainly a developer error
410 : : */
411 : 280 : void __phys_map_get(uint64_t topology_idx, uint64_t gcid, enum phys_map_type type,
412 : : int index, uint64_t *addr, uint64_t *size) {
413 : : const struct phys_map_entry *e;
414 : : uint64_t a;
415 : :
416 : 280 : if (!phys_map)
417 : 0 : goto error;
418 : :
419 : : /* Find entry in table */
420 : 13391 : for (e = phys_map->table; ; e++) {
421 : :
422 : : /* End of table */
423 : 13391 : if (phys_map_entry_null(e))
424 : 0 : goto error;
425 : :
426 : : /* Is this our entry? */
427 : 13391 : if (e->type != type)
428 : 12170 : continue;
429 : 1221 : if (e->index != index)
430 : 941 : continue;
431 : :
432 : : /* Found entry! */
433 : 280 : break;
434 : : }
435 : 280 : a = e->addr;
436 : 280 : a += topology_idx << (phys_map->chip_select_shift);
437 : :
438 : 280 : if (addr)
439 : 280 : *addr = a;
440 : 280 : if (size)
441 : 280 : *size = e->size;
442 : :
443 : 280 : prlog(PR_TRACE, "Assigning BAR [%"PRIx64"] type:%02i index:%x "
444 : : "0x%016"PRIx64" for 0x%016"PRIx64"\n",
445 : : gcid, type, index, a, e->size);
446 : :
447 : 280 : return;
448 : :
449 : 0 : error:
450 : : /* Something has gone really wrong */
451 : 0 : prlog(PR_EMERG, "ERROR: Failed to lookup BAR type:%i index:%i\n",
452 : : type, index);
453 : 0 : assert(0);
454 : : }
455 : :
456 : 0 : void phys_map_get(uint64_t gcid, enum phys_map_type type,
457 : : int index, uint64_t *addr, uint64_t *size)
458 : : {
459 : : struct proc_chip *chip;
460 : 0 : uint64_t topology_idx = gcid;
461 : :
462 : 0 : if (proc_gen >= proc_gen_p10) {
463 : 0 : chip = get_chip(gcid);
464 : 0 : topology_idx = chip->primary_topology;
465 : : }
466 : :
467 : 0 : return __phys_map_get(topology_idx, gcid, type, index, addr, size);
468 : : }
469 : :
470 : 3 : void phys_map_init(unsigned long pvr)
471 : : {
472 : 3 : const char *name = "unused";
473 : :
474 : 3 : phys_map = NULL;
475 : :
476 : 3 : if (proc_gen == proc_gen_p9) {
477 : 2 : switch(PVR_TYPE(pvr)) {
478 : 1 : case PVR_TYPE_P9P:
479 : 1 : name = "axone";
480 : 1 : phys_map = &phys_map_axone;
481 : 1 : break;
482 : 1 : default:
483 : 1 : name = "nimbus";
484 : 1 : phys_map = &phys_map_nimbus;
485 : : }
486 : 1 : } else if (proc_gen == proc_gen_p10) {
487 : 1 : name = "p10";
488 : 1 : phys_map = &phys_map_p10;
489 : : }
490 : :
491 : 3 : prlog(PR_DEBUG, "Assigning physical memory map table for %s\n", name);
492 : :
493 : 3 : }
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